Portable computers are power budget limited due to the requirement of being able to operate from batteries. Any technique which will lower the power requirement for the machine will, therefore, result in longer battery life. Memory can be a significant factor in power budget considerations, especially as more memory is required by emerging applications.
The systems designer has various choices for memory design. One choice is complementary metal oxide semiconductor (CMOS) static random access memory (SRAM). This device uses either a four or six transistor cell which implements a static storage mechanism requiring no refresh cycles. Six transistor (slow SRAM) devices have the added advantage of consuming very little power, but usually lag behind components such as DRAM in memory density. The per bit cost of SRAM is higher than that of DRAM.
Another choice is to use one transistor cell DRAMS. Unfortunately, the DRAM needs continuous refreshing which requires more power than a static CMOS implementation. Although the DRAM's simpler storage mechanism produces a lower cost per bit than SRAMS, its power requirements prevent it from adequately serving portable computers.
The requirement to refresh the DRAM is basic to the storage technique used in the DRAM cell. In this cell, data is stored as a charge of electrical energy trapped on a capacitor. Because the capacitor experiences leakage, the cell must be recharged or "refreshed" every so often. In today's technology, a 4 megabyte DRAM cell for example must be refreshed every six milliseconds at 70.degree. C.
Leakage of charge from the DRAM cell is mainly temperature dependent. Refresh times are always specified at the highest allowed operating temperature for the DRAM chip, as the leakage rate accelerates with increasing temperature. For every 12.degree. C. increase in temperature, the refresh rate must be doubled. If refresh rates can be adjusted for temperature, DRAM power consumption may be lessened, thereby allowing DRAMs to be candidates for use in portable computers and other devices which are battery powered.
U.S. Pat. No. 4,920,489 describes a circuit which adjusts the DRAM refresh rate based on the ambient temperature. This invention employs a thermistor in proximity to the DRAMs and a resistor to form a voltage divider, the output of which is digitized by an A/D converter inside the processor. The processor in turn controls the refreshing of the DRAMs at a rate controlled by a table accessed by the processor using the value digitized from the voltage divider. Thus the resolution of the refresh is equal to the table granularity.